// 64*32
module memory #(
    parameter InitEn = 0,
    parameter MEMFILE = "image.bin"
)
(
    input   logic               clk,

    input   logic   [7:0]       Mem_Addr,
    input   logic               Mem_Write,
    input   logic   [31:0]      M_W_Data,
    input   logic               Mem_Read,
    output  logic   [31:0]      M_R_Data
);


logic [31:0] mem [63:0];

// init
generate
    if(InitEn) begin : init_sram
        initial begin
            $readmemh(MEMFILE,mem);
        end
    end
endgenerate

// write
always_ff @( posedge clk ) begin
    if (Mem_Write) begin
        mem[Mem_Addr[7:2]] <= M_W_Data;
    end
end

// read
always_comb begin
    if(Mem_Read) begin
        M_R_Data = mem[Mem_Addr[7:2]];
    end
    else begin
        M_R_Data = 32'b0;
    end
end

// make verilator happy
logic [1:0] unused;
assign unused = Mem_Addr[1:0];


endmodule
